1. Technical Field
The present invention relates generally to semiconductor fabrication, and more particularly, to forming a dual-hybrid liner without exposing an underlying silicide layer to photoresist stripping chemicals.
2. Related Art
The application of stresses to field effect transistors (FETs) is known to influence their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents). One way to apply such stresses to a FET is the use of intrinsically-stressed barrier silicon nitride liners. For example, a tensile-stressed silicon nitride liner may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride liner may be used to cause compression in a PFET channel. However, tensile stress may degrade hole mobility and hence reduce PFET performance. Similarly, compressive stress may degrade electron mobility and hence worsen NFET performance. Accordingly, a dual/hybrid liner scheme is necessary to induce the desired stresses in an adjacent NFET and PFET.
In the formation of dual-hybrid silicon nitride liners for stress enhancement of NFET/PFET devices, the first deposited liner must be removed in one of the two FET regions by patterning and etching. One typical approach to forming a similar structure is disclosed in U.S. Patent Application Publication 2004/0029323 to Shimizu et al. In this disclosure, a silicon nitride film 13 is formed. In addition, in this disclosure, a silicon oxide film 13A (FIG. 4), e.g., P-TEOS or O3-TEOS, is formed as an insulating film over the silicon nitride film 13. Silicon nitride film 13 and silicon oxide film 13A are then exposed to a photo-etching technique to remove them from over the PFET (FIG. 4(b)). Next, another silicon nitride film 14 (FIG. 4(c)) is deposited as an insulating film, and then layer 14 is exposed to a photo-etching technique to remove it from over the NFET.
One shortcoming of the Shimizu et al. approach is that it requires exposure of an underlying silicide layer 12 adjacent the PFET to photoresist stripping chemicals in order to completely remove film 13 from the PFET region (FIG. 4(b)). Unfortunately, photoresist stripping chemicals typically include oxygen or ozone that can cause oxidation of silicide layer 12 and increased resistance. For example, a typical silicide layer normally has a resistance RS between about 6 ohm/sq and about 20 ohm/sq. By comparison, a slightly oxidized silicide layer may have a corresponding resistance RS between about 12 ohm/sq and about 40 ohm/sq. A much higher resistance or even open fail can occur when oxidation sensitive silicide is exposed. In technologies beyond 90 nm, which utilize ultra small gatelengths (e.g., <35 nm) and diffusion widths (e.g., <100 nm), such an increase in Rs is unacceptable because it will impact performance of the device. In addition to the above problem, exposure of silicide layer 12 to the photoresist stripping chemicals may result in an open circuit in silicide layer 12.
In view of the foregoing, a need exists for methods of fabricating a semiconductor device having a dual-hybrid liner in which the silicide layer is protected from photoresist stripping chemicals.